With the progress in the semiconductor integrated circuits reaching to ULSI (ultra large scale integration) level or even higher levels, the integrity of the integrated circuits has risen at an amazing rate. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. Taking DRAM (dynamic random access memories) for example, the increasing integrity in manufacturing has extended the capacity of a single chip to step from earlier 4 megabit to 16 megabit, and further to 256 megabit or even higher. Integrated circuit devices like transistors, capacitors, and connections must be greatly narrowed accompanying with the advancement. The increasing packing density of integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every element or device needs to be formed within a smaller area without influencing the characteristics and operations of the integrated circuits.
The demands on high packing density, low heat generation, and low power consumption devices with good reliability and long operation life must be maintained without any degradation in the function. These achievements are expected to be reached with the simultaneous developments and advancements in the photography, etching, deposition, ion implantation, and thermal processing technologies, the big five aspects of semiconductor manufacturing. The present technology research focus mainly on the sub-micron and one-tenth micron semiconductor devices to manufacture highly reliable and densely arranged integrated circuits.
Transistors, or more particularly metal oxide semiconductor (MOS) transistors, are the most important and frequently employed devices in integrated circuits. However, with the continuous narrowing of device size, the sub-micron scale MOS transistors have to face many risky challenges. As the MOS transistors become narrower and thinner accompanied by shorter channels, problems like the junction punchthrough, leakage, and contact resistance cause the reduction in the yield and reliability of the semiconductor manufacturing processes. The technologies like the self-aligned silicide (salicide) and the shallow junctions are utilized in combating the undesirable effects to manufacture the densely packing devices with good yield.
The electrostatic discharge (ESD) attacking has became a serious problem as the feature size of the MOS transistors has been scaled down. A semiconductor device having the input/output pad connections with external circuitry and devices is subject to the problem of the ESD. The ESD is easily conducted through the input/output and the power lead connections into the internal devices and causes some problems to semiconductor devices, especially serious ones like gate oxide breakdown and overheating damages.
The high voltage gradient generated between the contacts and the channels from the ESD causes the gate oxide electron injection and the carrier acceleration effect in the channels. The characteristics and operations of the devices are easily influenced by the inducing effects of the ESD. High levels of ESD with several hundred volts to a few thousand volts, which is easily transferred to the pins of an IC package during the handling, can bring permanent destruction to the internal devices. For preventing the devices from ESD damage built-in ESD protection circuits are connected between the input/output pads and the internal circuitry. A high level of abnormal discharge conducted into the pins of an IC package is kept out by the ESD protection circuits from flowing into the devices. The discharges are guided through the ESD protection circuits to the ground and the damage to the semiconductor devices is eliminated.
Several improvements in combating the ESD problem by forming the ESD protection devices have been provided previously. For example, U.S. Pat. No. 5,559,352 to C. C. Hsue and J. Ko disclosed a method of forming an ESD protection device with reduced breakdown voltage. Their invention employed a lightly implanted region of opposite conductivity type with the source/drain regions centered under the heavier implanted source/drain region. As another example, U.S. Pat. No. 5,498,892 to J. D. Walker and S. C. Gioia disclosed a lightly doped drain ballast resistor.
In their work, a field effect transistor with an improved electrostatic discharge (ESD) protection using a ballast resistor in the drain region is identified. The ballast resistor laterally distributes current along the width of the drain during an ESD pulse, which reduces local peak current density and reduces damage. But the operation speed problem with small feature size devices is still not solved. In addition, for applying most of the improvements, great efforts are needed with variations required in the semiconductor manufacturing circuits, thus increasing cost.
In manufacturing sub-micron feature size semiconductor devices, the salicide technology is a vital application to improve the operation speed of the ULSI/VLSI MOS devices. Unfortunately, there exists some trade-offs in employing the technologies like self-aligned silicide when facing the ESD problem. The devices with the self-aligned silicided contacts shows a worse ESD performance than the non-salicided devices. In general, thicker salicide has a negative effect on the ESD protection and makes semiconductor devices to be more sensitive to the ESD voltage and to be damaged more easily. The details are explored by the investigation of A. Amerasekera et al. ("Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN behavior with the ESDIEOS Performance of a 0.25 .mu.m CMOS Process.", IEDM Tech. Dig., p. 893, IEEE 1996) Their investigation presents the physical mechanisms involved in the degradation of ESD performance with the shallower junctions, the thicker salicides, and the different epitaxial thicknesses. The ESD challenge of salicide technology with the smaller scale devices can be clearly understood by referencing their work.